1. Field of the Invention
The invention relates to the field of networking. More specifically, the invention relates to the processing packets.
2. Background of the Invention
Packet processing may be implemented using a general purpose processor which performs all algorithms for delivering packets to their destination. However, more advanced packet processors separate “routing” from “switching.” The term “routing” used herein refers to determining the best path for packets to travel through a network from their source to their destination, while the term “switching” used herein refers to moving packets from one port to another, within a network element.
FIG. 1 shows a block diagram illustrating a prior art computer network. In this prior art figure, the backbone network 108 is made up of core routers 104a-b. The edge routers 102a-f connect the core routers 104a-b of the backbone network 108 to local area networks 106a-f. 
Core routers 104a-b, as compared to edge routers 102a-f, typically perform a lesser amount of packet processing. Typically, when packets reach core routers, advanced packet processing has been completed, leaving only basic packet processing for the core routers. For example, core routers mainly switch packets to other core routers on the backbone network; thus, performing only basic packet header modifications. Because core routers 104 mostly perform only basic packet processing, they can transmit packets faster than edge routers 102.
In contrast, edge routers 102a-d perform more complicated packet processing because they impose the backbone network's traffic constraints and other traffic control requirements on the local area networks 106a-f. For example, a backbone network owner may sell access to a backbone network to different local users. In FIG. 1, the local users make up the local area networks 106a-f. Local users may purchase access packages that allow access to the backbone network 108 at different levels of bandwidth. Edge routers 102 must enforce these bandwidth constraints upon the local area networks 106. For example, if a user's plan allows a user to transmit 10,000 Megabits per second to the backbone network 108, the edge routers 102 must determine whether the user is exceeding its bandwidth constraints, and drop packets accordingly. Because edge routers perform a wide variety of packet processing, they typically have greater processing capabilities, but lower packet throughput than core routers.
FIG. 2 shows a block diagram illustrating a prior art switching unit. The switching unit represents a set of one or more chips on a line card used for processing packets in a network element. The prior art switching unit of FIG. 2 includes classifier circuitry 202, which is connected to a processor queue 204. The processor queue 204 is connected to a processor array 206, which is connected to an output queue 212. The processor array executes software including packet processing software 208 and reorder buffering software 210.
In the prior art switching unit 200, incoming packets enter the classifying circuitry 202, wherein they are classified according to levels of needed processing. The packets are passed to the processor queue 204 before entering the processor array 206. In the processor array 206, the packet processing software 208 processes the packets according to their classifications. For example, a packet classified as a multicast packet is processed according to multicast procedures. Because packet processing may complete out-of-order for an ordered group of packets, and because it is advantageous to maintain order for groups of packets, the reorder buffering software 210 reorders the packets. The packets are transmitted to the output queue 210 and out of the switching unit 200.
A limitation of this prior art switching unit is that all packets travel the same path through the switching unit, regardless of the amount processing needed by each packet. As a result, this prior art switching unit has the disadvantage of sending packets needing very little processing through the processor array 206 and the software reorder buffer 208.